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confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 1 - 2004 magnachip semiconductor ltd. cmos image sensor HV7131R magnachip semiconductor ltd version 1.7
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 2 - 2004 magnachip semiconductor ltd. revision history revision issue date comments 1.0 2001-november-6 initial creation 1.1 2002-april-12 replaced adc to 10-bit resolution changed package specification changed pin configuration 1.2 2002-december-24 review datasheet & release 1.3 2002-december-30 add i/r reflow condition added 1.4 2003-march-12 40 pin pkg. drawing revision 1.5 2003.may-29 register revision 1.6 2004 march-26 electro-optical characteristic revision 1.7 2004 june-18 add spectral characteristics ? copyright 2004, magnachip semiconductor ltd. all right reserved.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 3 - 2004 magnachip semiconductor ltd. contents general description .................................................................................................................... 4 features ............................................................................................................................... ......... 4 block diagram ............................................................................................................................. 5 pin diagram ............................................................................................................................... ... 6 pixel array structure ............................................................................................................... 7 pin description ............................................................................................................................ 8 functional description ............................................................................................................... 9 register description ................................................................................................................. 11 frame timing ............................................................................................................................. 21 i2c chip interface ...................................................................................................................... 24 ac/dc characteristics .............................................................................................................. 26 mclk duty cycle......................................................................................................... 27 enb timi ng .................................................................................................................. 27 resetb ti ming ........................................................................................................... 27 electro-optical characteristics ................................................................................................ 30 electro-optical te st condition ............................................................................................. 30 soldering...................................................................................................................... ........ 30 package specification .............................................................................................................. 32 memo........................................................................................................................... ....... 33
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 4 - 2004 magnachip semiconductor ltd. general description HV7131R is a highly integrated single chip cmos color image sensor implemented by proprietary magnachip 0.30um cmos sensor process realizing high sensitivity and wide dynamic range. total pixel array size is 656x502, and 640x480 pixels are active. e ach active pixel composed of 4 transistors, it has a micro-lens to enhance sensitivity. and it converts photon energy to analog pixel voltage. on-chip 10-bit analog to digital converter (adc) are configured to digitize analog pixel voltage, and on-chip correlated double sampling (cds) scheme reduces fi xed pattern noise (fpn) dramatically. auto black level compensation (ablc) is using light blocking sh ield pixels which is placed top and bottom at core pixel to measure the black level and compensation . features z vga resolution z 5.04 m x 5.04 m active square pixel z 1/4.5 inch optical format z total pixel array : 656x502 / active pixel array : 640x480 z bayer rgb color filter array z micro-lens for high sensitivity z low power operation : voltage range : 2.6v - 3.0v z max frame rate : 30 frame/s at 25mhz master clock (vga) z package types : clcc 40ld, cob(chip-on-board), cof(chip-on-flex) z 10-bit digital image signal data bus z low fixed pattern noise by correlated double sampling z controllable full function through standard iic bus z external power down z programmable power down mode z auto black level compensation z flexible exposure time control z strobe control signal generation for frame capture mode z programmable video windowing z integrated 10bit analog to digital conversion z programmable frame rate up to 30frame/sec
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 5 - 2004 magnachip semiconductor ltd. block diagram 1. pga : programmable gain amplifier. 2. adc : analog to digital converter. 3. cds : correlated double sampling. 4. snr : sensor control digital logic.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 6 - 2004 magnachip semiconductor ltd. pin diagram 16 17 18 19 20 21 22 23 24 25 5 4 3 2 1 35 34 33 32 31 30 29 28 27 26 6 7 8 9 10 11 12 13 14 15 HV7131R clcc 40 pin top view nc nc mclk vclk agnd agnd avdd avdd nc nc strob vsync hsync dgndi sda dgndi sck dgndi enb dgndi nc resetb dvddi dvddc dgndc dgndi data[0] data[1] nc nc data[2] data[3] dgndi data[4] data[5] data[6] data[7] dgndi data[8] data[9] 40 39 38 37 36
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 7 - 2004 magnachip semiconductor ltd. pixel array structure r b g b g g r g r b g b g g r g ?? ?? r b g b g g r g r b g b g g r g ?? ?? metal shielded black level array[2 line] metal shielded black level array[2 line]
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 8 - 2004 magnachip semiconductor ltd. pin description pin type symbol description 1 g dgndi ground for i/o buffer. 2 i sck i2c clock input. 3 g dgndi ground for i/o buffer. 4 i enb enb signal enables sensor : high(sensor enabled), low(sensor disabled, external power down) 5 g dgndi ground for i/o buffer. 6~7 n nc no connection. 8 i mclk master input clock. 9 o vclk video output clock. 10~11 g agnd ground for analog block. 12~13 p avdd power for analog block. 14~15 n nc no connection. 16 o data[9] image output data bit 9. 17 o data[8] image output data bit 8. 18 g dgndi ground for i/o buffer. 19 o data[7] image output data bit 7. 20 o data[6] image output data bit 6. 21 o data[5] image output data bit 5. 22 o data[4] image output data bit 4. 23 g dgndi ground for i/o buffer. 24 o data[3] image output data bit 3. 25 o data[2] image output data bit 2. 26~27 n nc no connection. 28 o data[1] image output data bit 1. 29 o data[0] image output data bit 0. 30 g dgndi ground for i/o buffer. 31 g dgndc ground for internal digital block. 32 p dvddc power for internal digital block. 33 p dvddi power for i/o buffer. 34 i resetb sensor reset, low active. 35 n nc no connection. 36 o strobe strobe signal output. 37 o vsync video frame synchronization signal. / frame start output vsync is active at start of image data frame. 38 o hsync video horizontal line synchronization signal. / data is valid, when hsync is high. 39 g dgndi ground for i/o buffer. 40 b sda i2c standard data i/o port.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 9 - 2004 magnachip semiconductor ltd. functional description pixel architecture pixel architecture is a 4-transistor nmos pixel design. the additional use of a dedicated transfer transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved. sensor imaging operation imaging operation is implemented by the offset mechanism of integration domain and scan domain(rolling shutter scheme). first integrati on plane is initiated, and after the programmed integration time is elapsed, scan plane is initiated, then image data start being produced. integration time frame 0 time time integration plane frame 0 integration plane frame 1 scan plane frame 0 scan plane frame 1 frame 1 time
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 10 - 2004 magnachip semiconductor ltd. spectral characteristics hv7131g spectral response 0 0.2 0.4 0.6 0.8 1 1.2 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 ??? (nm) ???? b g r
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 11 - 2004 magnachip semiconductor ltd. register description register symbol address default description device id devid 00h 02h product identification, revision number. sensor control a sctra 01h 09h clkdiv[6:4], ablcen[3], pxlvs[2], xflip[1], yflip[0] sensor control b sctrb 02h 01h vclk disable[6], adcpwdn[5], black mode[4], sleep[3], vshsen[2], bldataen[1], strobeen[0] output inversion outiv 03h 00h byrdpcen[6], byrdpcth[5:4], clkhsc[3], invvsc [2], invhsc[1], invvclk[0] row start add upper rsau 10h 00h row start address upper byte[8] row start add lower rsal 11h 02h row start address lower byte[7:0] col. start add upper csau 12h 00h column start address upper byte[9:8] col. start add lower csal 13h 02h column start address lower byte[7:0] window height upper wihu 14h 01h window height upper byte[8] window height lower wihl 15h e2h window height lower byte[7:0] window width upper wiwu 16h 02h window width upper byte[9:8] window width lower wiwl 17h 82h window width lower byte[7:0] hblank time upper hblu 20h 00h hb lank time upper byte[15:8]. hblank time lower hbll 21h d0h hb lank time lower byte[7:0]. vblank time upper vblu 22h 00h vblank time upper byte[15:8]. vblank time lower vbll 23h 08h vblank time lower byte[7:0]. integration time high inth 25h 06h integration time [23:16] integration time middle intm 26h 5bh integration time [15:8] integration time low intl 27h 9ah integration time [7:0] pre-amp gain pag 30h 10h gain for pre-amp (0.5~16.5 times with 8bit resolution) [7:0] red color gain rcg 31h 10h gain for red pixel read-out (0.5~2 times with 6bit resolution) [5:0] green color gain gcg 32h 10h gain for green pixel read-out (0.5~2 times with 6bit resolution [5:0] blue color gain bcg 33h 10h gain for blue pixel read-out (0.5~2 times with 6bit resolution [5:0] analog bias control a actra 34h 17h cds bias [6:4], pga bias [3:0] analog bias control b actrb 35h 7fh reset clamp [7:4], adc bias [3:0] black level threshold blcth 40h ffh auto black level pixel threshold value initial adc offset red oredi 41h 7fh initial adc offset red initial adc offset green ogrni 42h 7fh initial adc offset green initial adc offset blue oblui 43h 7fh initial adc offset blue
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 12 - 2004 magnachip semiconductor ltd. device id [devid : 00h : 02h] 7 6 5 4 3 2 1 0 product id revision number 0 0 0 0 0 0 1 0 high nibble represents sensor array resoluti on, low nibble represents revision number. sensor control a [sctra : 01h : 09h] 7 6 5 4 3 2 1 0 reserved clkdiv ablc en pxlvs x flip y flip - 0 0 0 1 0 0 1 clock division device input master clock(imc) for internal use. internal divided clock frequency(dcf) is defined as master clock frequency(mcf) divided by specified clock divisor. dcf is as follows 000 : dcf = mclk, 001 : dcf = mclk/2, 010 : dcf = mclk/4 011 : dcf = mclk/8, 100 : dcf = mclk/16, 101 : dcf = mclk/32 110 : dcf = mclk/64, 111 : dcf = mclk/128, ablc en 0 : auto black level compensation disable 1 : auto black level compensation enable pxlvs vblank unit : vblank time value 0 : lcf unit 1 : scf unit x-flip 0 : normal. 1 : image is horizontally flipped. y-flip 0 : normal. 1 : image is vertically flipped. sensor control b [sctrb : 02h : 01h]
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 13 - 2004 magnachip semiconductor ltd. 7 6 5 4 3 2 1 0 reserved vclk adc pwdn black mode sleep mode vshsen bldataen strobeen - 0 0 0 0 0 0 1 vclk when this bit is high video output clock(vclk) disable adcpwdn when this bit is high adc block goes to power down black mode black and white mode : red and blue gain use the green gain when this bit is set to high. 0 : color mode 1 : black and white mode sleep mode software power down 0 : software power down mode off. 1 : software power down mode on. all internal digital block goes to sleep mode with this bit set to high vshsen hsync in vblank : vblank is equivalent to vsync, and hsync is the inversion of hblank, and this signal control whether hsyn c is active or not when vblank unit is lcf. 0 : there are no valid hsync signals during valid vsync signal. 1 : there are valid hsync signals during valid vsync signal. number of valid hsync is same as number of vblank register when vsync unit is line unit. do not use this mode when vsync unit is pixel unit vsync (vblank) hsync bldataen black level data enable : hsync is generat ed for light-shielded pixels in 4 lines.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 14 - 2004 magnachip semiconductor ltd. strobeen strobe enable : when stroben is high strobe pin will indicates when strobe light should be splashed in dark environment to get adequate lighted image output inversion [outiv : 03h : x0h] 7 6 5 4 3 2 1 0 reserved clocked hsync vsync inversion hsync inversion vclk inversion - - - - 0 0 0 0 clocked hsync in hsync, vclk is embedded, that is, hsync is toggling at vclk rate during normal hsynv time vsync inversion vsync output polarity is inverted hsync inversion hsync output polarity is inverted vclk inversion hsync output polarity is inverted row start address upper [rsau : 10h : x0h] 7 6 5 4 3 2 1 0
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 15 - 2004 magnachip semiconductor ltd. reserved rsa[8] - - - - - - - 0 row start address low [rsal : 11h : 02h] 7 6 5 4 3 2 1 0 rsa[7:0] 0 0 0 0 0 0 1 0 row start address register defines the row start address of image read out operation. column start address upper [csau : 12h : x0h] 7 6 5 4 3 2 1 0 reserved csa[9:8] - - - - - - 0 0 column start address low [csal : 13h : 02h] 7 6 5 4 3 2 1 0 csa[7:0] 0 0 0 0 0 0 1 0 column start address register defines the co lumn start address of image read out operation. window height upper [wihu : 14h : x1h] 7 6 5 4 3 2 1 0 reserved wih[8] - - - - - - - 1 window height low [wihl : 15h : e2h] 7 6 5 4 3 2 1 0 wih[7:0] 1 1 1 0 0 0 1 0
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 16 - 2004 magnachip semiconductor ltd. window height register defines the height of image read out operation. window width upper [wiwu : 16h : x2h] 7 6 5 4 3 2 1 0 reserved wiw[9:8] - - - - - - 1 0 window width low [wiwl : 17h : 82h] 7 6 5 4 3 2 1 0 wiw[7:0] 1 0 0 0 0 0 1 0 window width register defines the width of image read out operation. horizontal blanking time upper [hblu : 20h : 00h] 7 6 5 4 3 2 1 0 hblank time [15:8] 0 0 0 0 0 0 0 0 horizontal blanking time low [hbll : 21h : d0h] 7 6 5 4 3 2 1 0 hblank time [7:0] 1 1 0 1 0 0 0 0 hblank time register defines data blank time between current line and next line by using sensor clock period unit (1/scf), and should larger then 208(d0h) vertical blanking time high [vblu : 22h : 00h] 7 6 5 4 3 2 1 0 vblank time[15:8] 0 0 0 0 0 0 0 0
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 17 - 2004 magnachip semiconductor ltd. vertical blanking time low [vbll : 23h : 08h] 7 6 5 4 3 2 1 0 vblank time[7:0] 0 0 0 0 1 0 0 0 vblank time register defines active hi gh duration of vsync output. active high vsync indicates frame boundary between continuous fram es for vsync-hsync timing relation in the frame transition, please refer to frame timing section integration time high [inth: 25h : 06h] 7 6 5 4 3 2 1 0 integration time [23:16] 0 0 0 0 0 1 1 0 integration time middle [intm: 26h: 5bh] 7 6 5 4 3 2 1 0 integration time [15:8] 0 1 0 1 1 0 1 1 integration time low [intl: 27h: 9ah] 7 6 5 4 3 2 1 0 integration time [7:0] 1 0 0 1 1 0 1 0 integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal adc processing. integration time is equivalent to exposure time of genera l camera. so that integration time need to be increased in dark environment and decreased in bright environment. maximum value of integration time is (2 24 -1) x sensor clock period (80ns, sc f 12.5mhz @ dcf 25mhz) = 1.34sec
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 18 - 2004 magnachip semiconductor ltd. preamp gain [pag : 30h : 10h] 7 6 5 4 3 2 1 0 preamp gain 0 0 0 1 0 0 0 0 preamp gain is common gain for r, g, b channel and used for auto exposure control. programmable range is from 0.5x ~ 16.5x. default gain is 1.5x. gain = 0.5 + b<7:0>/16 red color gain [rcg : 31h : 10h] 7 6 5 4 3 2 1 0 reserved red color gain - - 0 1 0 0 0 0 green color gain [gcg : 32h : 10h] 7 6 5 4 3 2 1 0 reserved green color gain - - 0 1 0 0 0 0 blue color gain [bcg : 33h : 10h] 7 6 5 4 3 2 1 0 reserved blue color gain - - 0 1 0 0 0 0 there are three color gain registers for r, g, b pixels, respectively. r, g, b color gain are used to amplify r, g, b channel. programmable range is from 0.5x ~ 2.5x. default gain is 1x. gain = 0.5 + b<5:0>/32 analog bias control a [actra : 34h : 17h] 7 6 5 4 3 2 1 0 reserved cds bias pga bias - 0 0 1 0 1 1 1 pga bias
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 19 - 2004 magnachip semiconductor ltd. controls the amount of current in internal amplifie r bias circuit to amplify pixel output effectively. the larger register value increases the amount of current cds bias controls the amount of current in internal cds bi as circuit to amplify pixel output effectively. the larger register value increases the amount of current analog bias control b [actrb : 35h : 7fh] 7 6 5 4 3 2 1 0 reset clamp adc bias 0 1 1 1 1 1 1 1 reset level clamp because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. to solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. reset level clamp controls the reset data voltage to pr event inversion of extremely bright image. the larger register value clamps the reset data level at highest voltage level. default value is 7 to clamp the reset data level at appropriate voltage level. adc bias adc bias controls the amount of current in adc bias circuit to operate adc effectively. the larger register value increase the amount of current black level threshold [blcth : 40h : ffh] 7 6 5 4 3 2 1 0 black level threshold 1 1 1 1 1 1 1 1 the register specifies the maximum value, whic h determines whether light shielded pixel output, is valid. when light shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 20 - 2004 magnachip semiconductor ltd. initial adc offset red [oredi : 41h : 7fh] 7 6 5 4 3 2 1 0 initial adc offset red 0 1 1 1 1 1 1 1 initial adc offset green [ogrni : 42h : 7fh] 7 6 5 4 3 2 1 0 initial adc offset green 0 1 1 1 1 1 1 1 initial adc offset blue [oblui : 43h : 7fh] 7 6 5 4 3 2 1 0 initial adc offset blue 0 1 1 1 1 1 1 1 * update adc offset = - (average ? initial adc offset) these values are using black level compensation in active pixel. average value is measured and calculated at li ght shielded pixel with ablcen is active.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 21 - 2004 magnachip semiconductor ltd. frame timing for clear description of frame timing, clocks? ac ronym and relation are reminded in here again. < clock acronym definition > mcf(master clock frequency) : mclk dcf(divided clock frequency) : mcf/clock division scf(sensor clock frequency) : dcf/2 vcf( video clock frequency) : scf lcf(line clock frequency) : 1/(hblanj period + hsync period (hblank time + video width time) scp(sensor clock period) = 1/scf, lcp(line clock period) = 1/lcf < frame time calculation > ablc time = 4lcp * (hblank + 512 scp) core frame time = idle slot + video height * lcp real frame time = integration time + vblank * lcp for integration time > core frame time = core frame time + vblank * lcp for integration time <= core frame time hold slot time = integration time - core fram e time for integration time > core frame time = 0 for integration time <= core frame time where idle slot is 1lcp.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 22 - 2004 magnachip semiconductor ltd. 1. vga size when programmable window is disabled and ablc enable vga frame timing related parameters master clock frequency(mcf) 25mhz clock division mcf/1 = 25mhz sensor clock frequency(scf) dcf/2 =12.5mhz sensor clock period(scp) 1/12.5mhz = 80ns hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 848 scps ablc enable programmable window off if integration time < core frame time, real frame time is 2(208 + 640)scps + 4(208 + 512)scps + 480(208 + 640)scps + 8(208 + 640)scps = 418400 scps =418400 x 80ns = 33.47msec = 29.87fps else real frame time is integration time * scps + 8 * (208 +640) scps. hold slot in frame timing appears only if int egration time is larger then core frame time 2. vga size when programmable window is disabled and ablc disable lcp ( 848scps ) idle slot ( 2lcp ) hold slot integration time ? core frame time vblank[vsync] (8lcp) hblank (208 scps) hsync(640 scps) active data : 640 ea real frame time core frame time 480 lcps video height 4th line data flow hblank (208 scps) hsync ( 640 scps ) vclk=12.5[mhz] lcp = 848 scps 5th line data flow 482th line data flow 483th line data flow video width ( 640scp ) 0~3 line data flow for ablc a blc time hi - z valid data data[9:0]
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 23 - 2004 magnachip semiconductor ltd. vga frame timing related parameters master clock frequency(mcf) 25mhz clock division mcf/1 = 25mhz sensor clock frequency(scf) dcf/2 =12.5mhz sensor clock period(scp) 1/12.5mhz = 80ns hblank value 208 vblank value 8 vsync mode line mode line clock period(lcp) 848 scps ablc disable programmable window off if integration time < core frame time, real frame time is 2(208 + 640)scps + 480(208 + 640)scps + 8(208 + 640)scps = 415520 scps =415520 x 80ns = 33.24msec = 30fps else real frame time is integration time * scps + 8 * (208 +640) scps. hold slot in frame timing appears only if int egration time is larger then core frame time i2c chip interface lcp ( 848scps ) idle slot ( 2lcp ) hold slot integration time ? core frame time vblank[vsync] (8lcp) hblank (208 scps) hsync(640 scps) active data : 640 ea real frame time core frame time 480 lcps video height 4th line data flow hblank (208 scps) hsync ( 640 scps ) vclk=12.5[mhz] lcp = 848 scps 5th line data flow 482th line data flow 483th line data flow video width ( 640scp ) hi - z valid data data[9:0]
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 24 - 2004 magnachip semiconductor ltd. the serial bus interface consists of the sda(se rial data) and sck(serial clock) pins. hv7131gr sensor can operate only as a slave. the sck only controls the serial interface. however, mclk should be supplied and reset should be high signal during controllin g the serial interface. the start condition is that logic transition (h igh to low) on the sda pin while the sck pin is at high. the stop condition is that logic transition (low to high) on the sda pin while the sck pin is at high. to generate acknowledge signal, the sens or drives the sda low when the sck is high. every byte consists of 8 bits. each byte transferred on the bus must be followed by an acknowledge. the most significant bit of the byte should always be transmitted first. register write sequences one byte write s 22h a 01h a 03h a p *1 *2 *3 *4 *5 *6 *7 *8 set "sensor control a" register into window mode *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 01h [sub-address] *5. read: acknowledge from sensor *6. drive: 03h [video mode : cif] *7. read: acknowledge from sensor *8. drive: i2c stop condition 1 2 8 9 a ck msb lsb sd a sck start 1 2 8 9 a ck stop
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 25 - 2004 magnachip semiconductor ltd. multiple byte write using auto address increment s 22h a 10h a 00h a 64h a p *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 set "hsync blanking high/low" register as 0064h with auto address increment *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device address + r/w bit] *3. read: acknowledge from sensor *4. drive: 10h [sub-address] *5. read: acknowledge from sensor *6. drive: 00h [hsync blanking high] *7. read: acknowledge from sensor *8. drive: 64h [hsync blanking low] *9. read: acknowledge from sensor *10. drive: i2c stop condition register read sequence s 22h a 01h a s 23h a 13h a p *1 *2 *3 *4 *5 *6 *7 *8 *9 *1 0 *11 read "sensor control a" register from hv7131gr *1. drive: i2c start condition *2. drive: 22h(001_0001 + 0) [device a ddress + r/w bit(be careful. r/w=0)] *3. read: acknowledge from sensor *4. drive: 01h [sub-address] *5. read: acknowledge from sensor *6. drive: i 2 c start condition *7. drive: 23h(001_0001 + 1) [device a ddress + r/w bit(be careful. r/w=1)] *8. read: acknowledge from sensor *9. read: read ?13h(value of sens or control a) ? from sensor *10. drive: acknowledge to sensor. if there is more data bytes to read, sda should be driven to low and data read states(*9, *10) is repeated. otherwise sda should be driven to high to prepare for the read transaction end. *11. drive: i2c stop condition ac/dc characteristics
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 26 - 2004 magnachip semiconductor ltd. absolute maximum ratings symbol parameter units min. max. vdpp digital supply voltage volts -0.3 7.0 vapp analog supply voltage volts -0.3 7.0 vipp input signal voltage volts -0.3 7.0 top operating temperature c -10 50 tst storage temperature c -30 80 caution: stresses exceeding the absolute maximum ratings may induce failure. dc operating conditions symbol parameter units min. max. load[pf] notes v dd internal operation supply voltage volt 2.6 3.0 v ih input voltage logic "1" volt 2.0 3.0 6.5 v il input voltage logic "0" volt 0 0.8 6.5 v oh output voltage logic "1" volt 2.15 60 at ioh = -1ma v ol output voltage logic "0" volt 0.4 60 i oh output high current ma -4 60 i ol output low current ma 4 60 t a ambient operating temperature celsius -10 50 ac operating conditions symbol parameter max operation frequency units notes mclk main clock frequency 25 mhz 1 sck i 2 c clock frequency 400 khz 2 i normal power consumption in normal mode 30.953 @ 30fps, 25mhz ma i down_hard power consumption in hard power down mode 0.095 @ 25mhz ua i down_soft power consumption in soft power down mode 208.815 @ 25mhz ua 1. mclk may be divided by internal clock divisi on logic for easy integration with high speed video codec. 2. sck is driven by host processor. for the deta il serial bus timing, refer to i2c chip interface section input ac characteristics
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 27 - 2004 magnachip semiconductor ltd. mclk duty cycle t a = 40% ~ 60% of t mclk, t b = 40% ~ 60% of t mclk , t a + t b = t mclk enb timing enb pin enables sensor. if you set enb pin to low, sensor goes to power down. though sensor remains power down, you can program the regi sters by above iic protocol. after enb is changed to high, the registers that you set in power down are newly updated. if you want software power down with enb pin high, set sleep mode in sctrb(02h)register. resetb timing resetb pin initializes the registers to default val ue. when resetb pin is low, initialization is done. hv7131gr is automatically reset the chip when power on. we recommend to initia lize the registers by using resetb pin. t r : resetb valid minimum time: 10 mclk periods. output ac characteristics all output timing delays are measured with output l oad 60[pf]. output delay includes the internal mclk t mclk t b t a v dd / 2 t r resetb mclk sensor ready to operate enb vsync hsync data[9:0] vclk
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 28 - 2004 magnachip semiconductor ltd. clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. due to the variable valid time delay of the output, rgb output signals data[9:0], hsync, and vsync may be latched in the negative edge of vclk for the stable data transfer betwe en the image sensor and video codec. data[9:0] vclk (non inverted) x data 0 data 1 data 2 hsync data 3 minimum delay : 0.5xmaster clock period i2c bus timing sda sck stop start t buf t low t r t hd; s ta t hd; d at t high t su; d at t su; s ta t su; s to stop start t f t hd; s ta
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 29 - 2004 magnachip semiconductor ltd. parameter symbol min. max. unit sck clock frequency f sck 0 400 khz time that i 2 c bus must be free before a new transmission can start t buf 1.2 - us hold time for a start t hd ;s ta 1.0 - us low period of sck t low 1.2 - us high period of sck t high 1.0 - us setup time for start t su ;s ta 1.2 - us data hold time t hd ;d at 1.3 - us data setup time t su ;d at 250 - ns rise time of both sda and sck t r - 250 ns fall time of both sda and sck t f - 300 ns setup time for stop t su ;s to 1.2 - us capacitive load of sck/sda c b - - pf
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 30 - 2004 magnachip semiconductor ltd. electro-optical characteristics parameter units min. typical max. note 2053.9 2480.482 3121.600 green 1356 1657.460 2093.500 red sensitivity mv / lux x sec 1362.3 1656.700 2074.100 blue dark signal code 0.000 10.728 31.990 1022.980 1023.000 1023.000 green 1022.990 1023.000 1023.000 red output saturation signal mv 1023.000 1023.000 1023.000 blue 4.428 6.627 11.861 dynamic dvdd power consumption ma 19.572 24.326 30.009 dynamic avdd 0.000 0.005 27.130 static dvdd power consumption ua 0.000 0.090 29.610 static avdd 182.160 208.806 259.660 sleep dvdd power consumption ua 0.00 0.009 17.580 sleep avdd - color temperature of light source: 3200k / ir cu t-off filter (cm-500s, 1 mm thickness) is used. soldering infrared(ir) / convection solder reflow condition parameter convection or ir/convection average ramp-up rate(183 c to peak) 3 c / second max. preheat temperature 125(25) c 120 second max. temperature maintained above 183 c 60 ? 150 second time within 235 c of actual peak temperature 10 ? 20 second peak temperature range (220 +5/-0) c or (235 +5/-0) c ramp-down rat 6 c / second max. time 25 c to peak temperature 6 minute
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 31 - 2004 magnachip semiconductor ltd. 30 60 90 120 180 210 240 270 300 330 360 150 125 180 235 temp.( c ) time(seconds) 120 sec. max 60 ~ 150 sec. max 10 ~ 20 sec.
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 32 - 2004 magnachip semiconductor ltd. package specification - 40 pin clcc - -
confidential HV7131R this document is a general product description and is subject to change without notice. magnachip semiconductor ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 33 - 2004 magnachip semiconductor ltd. memo magnachip semiconductor ltd. * contact point * cis marketing team 15floor, magnachip youn gdong bldg. 891 daechi-dong kangnam-g u seoul 135-738 re public of korea tel: 82-2-3459-3374 fax: 82-2-3459-5580 e-mail : hanho.lee@magnachip.com

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